# microBMS design concept



## jddcircuit (Mar 18, 2010)

I wanted to share a simulation I just did for a sensor design that can detect whether the individual cell voltages are Within Operating Limits.

I titled this thread microBMS in relation to the popular miniBMS since it is similar in several respects except it will draw sub 10micro amp quiesent current. It will take 100 years to create an imbalance in the stack from this low parasitic load.

The normally closed single wire current path is created using PMOS transistors in the daisy chain path. An opto isolated control board can activate and sense this current path in a pulsed fashion to conserve power draw from the cells. If all sensors are in range then the current passes all the way through the chain and is sensed by the control board end of chain. If any cell is out of range then it shunts the current locally and the control board does not sense it end of chain indicating a cell is out of range.

The control board does not know which cell is out of range but the LEDS in line with the sample current path will light up to the sensor that is shunting. This should provide adequate visual for troubleshooting or maintenance.

Here is the schematic of a single cell module. The resistor divider can be selected to vary the operating range. The hysteresis voltage divider is also a point of tweaking the operation.








Here is 4 modules chained together and a representation of the opto isolated control circuit. Also one of the cells is made as a variable voltage that will vary in and out of the operating limits for simulation purposes.








Here is the simulation of the daisy chain circuit. I am showing currents at several of the nodes. You can see that the current gets interrupted when the alternating voltage goes out of range.








Let me know what you think. I think this could develop into something usable. I am picturing it being a backup detection for grossly out of range cell conditions. Pack voltage and Ah counting could still be the norm for pack use but with this additional safety net at the cell level.

Thanks
Jeff


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## jddcircuit (Mar 18, 2010)

I made some changes.
I added a First(F) connection for the top of chain that is current limited. I noticed the way it was connected before would not work if the first circuit module was out of range.

I added some notes showing the HVC and LVC trip points.


























Jeff


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## jddcircuit (Mar 18, 2010)

I made some more changes and I added some explanation.














In the simulation the circuit only draws 5 to 6 micro amps when not being sampled by the controller.

The controller will cause a 6mA sample current to pass through the daisy chain. The duration of this sample pulse is up to the user but it can be minimized to not discharge the pack. However it equally discharges the pack when all cell voltages are in range. The LED is in series with this sampling current. If more current is desired then reduce the series resistor R6.

The HVC and LVC and hyst are selected with the resistor dividers. I haven't spent any time selecting standard values or tweaking the details. These are here as place holders to demonstrate the function.

I think the function is unique in how it diverts the sampling current when it is out of range.

Check out the simulation signal graphs. I add some cursors to show the HVC and LVC points.
The green signal is the current into the N pin of the top module.
The blue signal is the current out of the S pin of the bottom module.
The red signal is the voltage of a single cell that I am using for demonstration.
The blue signal shows that the current does not exit the end of chain when the cell voltage is out of range.

The LED is for indicating the first cell module that is out of range. The controller can activate a persistent sample current and all of the LEDS will light up until the faulting module is reached. All LEDs following the shunting module will remain OFF.

You can also notice the hysteresis effect depending on the direction of cell voltage change.







Thanks
Jeff


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## jddcircuit (Mar 18, 2010)

Another cool thing to note about this configuration is that if there is a break in the daisy chain wire the LEDs will light up to the point of the break helping in quick troubleshooting.


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## jddcircuit (Mar 18, 2010)

I like this one even better.
The LT6700 works down to a lower voltage and has the hysteresis built in.








I am thinking that the controller could apply the daisy chain current continuously whenever the car was driving or the battery is charging. A latch at the end of chain could capture any out of range event to be handled accordingly.

When the battery is idle the monitoring circuits will be quiet and draw very little current from the pack.


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## kennybobby (Aug 10, 2012)

That's a really clever circuit--i like it too.

Do you think the D2 diode would ever get biased enough to conduct--it may not be necessary.


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## PStechPaul (May 1, 2012)

The idea has some merit, but I think it will need some refinements to make it practical. Putting the battery directly to the power pins of the comparator may be a problem, especially if there is a fault or bad connection. A BMS that connects only with a high value resistor is intrinsically safe, whereas in this case there should be a fuse or some other way to limit fault current. The comparator is a $1.50 part from Digikey in 100 pc quantity, and I could not find the MOSFET.

With the PMOS gate connected to the open drain outputs of the comparator, it seems that it would be essentially undriven until the comparator sets an output low. Also the voltages on each element of the daisy-chain may not balance well, and the MOSFET is only a 7 volt part.

There have been other ideas proposed for similar BMS systems, with extensive analysis and explanation of theory of operation. I haven't fully examined your circuit, and maybe it's OK. But there are a lot of things to consider. Thanks for your contribution.


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## jddcircuit (Mar 18, 2010)

kennybobby said:


> That's a really clever circuit--i like it too.
> 
> Do you think the D2 diode would ever get biased enough to conduct--it may not be necessary.


If the S pin is disconnected then the current coming from the N pin needs somewhere to go. It will conduct through D2. Otherwise the voltages across the PMOS transistors will increase beyond their limits.

Thanks for your interest


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## jddcircuit (Mar 18, 2010)

PStechPaul said:


> The idea has some merit, but I think it will need some refinements to make it practical. Putting the battery directly to the power pins of the comparator may be a problem, especially if there is a fault or bad connection. A BMS that connects only with a high value resistor is intrinsically safe, whereas in this case there should be a fuse or some other way to limit fault current. The comparator is a $1.50 part from Digikey in 100 pc quantity, and I could not find the MOSFET.
> 
> With the PMOS gate connected to the open drain outputs of the comparator, it seems that it would be essentially undriven until the comparator sets an output low. Also the voltages on each element of the daisy-chain may not balance well, and the MOSFET is only a 7 volt part.
> 
> There have been other ideas proposed for similar BMS systems, with extensive analysis and explanation of theory of operation. I haven't fully examined your circuit, and maybe it's OK. But there are a lot of things to consider. Thanks for your contribution.


I added some input filter/buffering. Since the circuit draws less than 10u, and 1k input resistor only drops 10mV. The simulation still runs fine with the added 1kohm and 1uF input filter.










I randomly picked the diode and pmos devices off the LTSpice model list for simulation purposes. Feel free to recommend a low cost available component. The MOSFET just needs a threshold voltage not too high in relation to the minimum cell voltage. 

Thanks for giving it your review.
Jeff


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## jddcircuit (Mar 18, 2010)

Ok now it is starting to blow my low component count up a bit.

The 1kohm resistor on the supply is creating a problem. I assumed that since the outputs were open drain that they could sink the daisy chain current without loading the supply voltage. I don't have components to test but the simulation model did not like it.

I added an emitter follower and that relieved the IC from getting loaded when it was shunting the current flow.









The M node is only a sub circuit meter point for my simulation debugging. The F node is being used as the First board input. In my daisy chain simulation I am using a current source entering the first board at this point (ie 10mA). This current source will be part of the controller interface TBD.

Jeff


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## jddcircuit (Mar 18, 2010)

ADCMP670 is drop in replacement for the LT6700-1

perhaps it has pure open drain outputs and won't need the emitter follower.


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## jddcircuit (Mar 18, 2010)

TPS3700 seems to be equivalent function but is less expensive


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## PStechPaul (May 1, 2012)

I would suggest using an optoisolator for the cell error detection. However, with the usual NO output type, they would need to be daisy-chained in parallel, rather than series, and it would be turned ON to indicate a fault. There can be an LED in the drive circuit to give visual indication. There are optocouplers for about $0.20 in 100 pc quantity:
http://www.mouser.com/ProductDetail/CEL/PS2561A-1-V-A/?qs=sGAEpiMZZMviNQmaL%2fXs4opHE8u3maL2

You can get an optocoupler (actuallly SSR) with a NC output, for about $1:
http://www.mouser.com/ProductDetail...EpiMZZMsUriz2CNI3E%2bJNr%2bghbhd0dnKWwYoS82M=
It will handle 60V and 150 mA, so it may be able to drive a larger relay directly.

One of my ideas was to use an inexpensive 8 pin PIC for the voltage sensing and signalling functions. It can be programmed so that it goes into sleep mode (20 nA) and wakes up every few seconds to take a quick reading. If the voltage is out of spec, it would stay on, in which case it would draw a little more current, and the LED and optocoupler can be pulsed to reduce the average current draw. I would suggest a PIC12F1822, which is only about $0.83/100.
http://www.mouser.com/ProductDetail...=sGAEpiMZZMvqv2n3s2xjsW2MXUmlRZqtXS7oohoqh6w=

There are ways to achieve even more functionality by using a daisy-chain communication system where each PIC is assigned an address of 01h-0ffh for a total of 254 cell capacity, and a master controller can send a request for information that is passed on down the chain untill it reaches the address selected. Then the requested information (cell voltage) is added to the packet and it continues to propagate back to the master controller. Also, any one of the PICs can initiate an error message. The data packet can be detected by one of the pins which can initiate a wake-up from sleep, for minimal current drain between operations.


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## jddcircuit (Mar 18, 2010)

PStechPaul said:


> I would suggest using an optoisolator for the cell error detection. However, with the usual NO output type, they would need to be daisy-chained in parallel, rather than series, and it would be turned ON to indicate a fault. There can be an LED in the drive circuit to give visual indication. There are optocouplers for about $0.20 in 100 pc quantity:
> http://www.mouser.com/ProductDetail/CEL/PS2561A-1-V-A/?qs=sGAEpiMZZMviNQmaL%2fXs4opHE8u3maL2
> 
> You can get an optocoupler (actuallly SSR) with a NC output, for about $1:
> ...


Paul,

These are good suggestions but so we are on the same page. The primary goal for me is to not create or contribute to cell imbalance. I want to minimize the parasitic load of each module and more importantly to minimize the difference in current draw of each monitoring module.

The micro per cell might work and I have seen threads that discuss this approach. I don't think I have seen a tried and true communication link and protocol that also considers equally distributed power consumption but I am open to discuss it.

In my window comparator design there is a condition where the cells are experiencing different currents. This happens when a cell is out of range and the controller is sampling. The way the system will minimize the time spent in this imbalance condition is with the controller sampling frequency which seems pretty straight forward to me.

In this thread I am investigating a most basic approach to provide a most basic status.

Thanks
Jeff


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## jddcircuit (Mar 18, 2010)

kennybobby said:


> When in normal mode the comparator outputs will be high, which turns on the open drain fets and sinks or shunts the daisy-chain current.
> 
> When in HVC or LVC modes the comparator outputs will be low, which is a high impedance state for the open-drain fets, so the chain current will be passed on to the next daisy.
> 
> Do i have the logic inverted, or how does the 6mA make it to the end to fire off the opto?


I don't think it is inverted. Look at post #4. The simulation signal plots show the current end of chain. You can see the 6ma passes through when the cell voltage is within range.


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## PStechPaul (May 1, 2012)

From what I see, the comparator outputs are OFF in the normal range, and ON (low) either above or below the limits. When they are ON, the PNP transistor Q1 is ON, with base shunted to collector, and current will flow from "N" through the 100 ohm resistor and LED D1 and Q1 and into the junction of the cell being measured and the cell below it.

When the comparator is OFF, the OC or OD outputs are essentially floating, which means that Q1 will have an open base. This will normally result in it being OFF, so the source of MOSFET M1 will be open, while the gate is at GND, or the junction between the measured cell (-) and the next cell (+), or the bottom of the pack if this is the last cell. Due to leakage, it is more likely that the S-G junction will go to a voltage lower than the ON threshold, and M1 will probably be OFF. 

If M1 is OFF, and the other circuits are ON, the full pack voltage will be applied between drain and gate. But this may be limited by the intrinsic S-D body diode, so the current will be shunted through that.

It is difficult to visualize with the two separate schematics. It would be much better to make one schematic with at least two or three of the circuits, and then analyze the current flow and general operation. In any case, if any one of these modules actually impedes the current flow in the sense circuit, the MOSFET must see the full pack voltage, and since low threshold MOSFETs tend to have low voltage ratings (12-20V), or else may be rather expensive for one that will reliably handle a typical pack voltage of 48 VDC or more. I'm not going to do the simulation, so it is up to you to verify your assertions. It would also be helpful if you posted the ASCII file for your LTSpice simulation, in which case I might be interested enough to see if my concerns have merit.


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## jddcircuit (Mar 18, 2010)

PStechPaul said:


> From what I see, the comparator outputs are OFF in the normal range, and ON (low) either above or below the limits. When they are ON, the PNP transistor Q1 is ON, with base shunted to collector, and current will flow from "N" through the 100 ohm resistor and LED D1 and Q1 and into the junction of the cell being measured and the cell below it.
> 
> When the comparator is OFF, the OC or OD outputs are essentially floating, which means that Q1 will have an open base. This will normally result in it being OFF, so the source of MOSFET M1 will be open, while the gate is at GND, or the junction between the measured cell (-) and the next cell (+), or the bottom of the pack if this is the last cell. Due to leakage, it is more likely that the S-G junction will go to a voltage lower than the ON threshold, and M1 will probably be OFF.
> 
> ...


Your assumptions are incorrect.

Every mosfet only sees a single cell voltage. It took me a while to get my head around it but it does work. I have built some other circuits using this stack mosfet arrangement in a series of cells. I have tested 50 cells in series sending actual cell voltage data through the data link.

No need for you to do a simulation. Already did it.

Thanks


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## PStechPaul (May 1, 2012)

What may happen is that the daisy chain circuit current gets shunted into the bottom part of the pack, rather than continuing through the circuits. Also, it may be that since at least one of the nodes of the daisy chain elements is clamped at or near the pack voltage at that point, the MOSFETs never see a higher voltage. I think it is possible to design the circuit more effectively using just the OD outputs of the comparators connected to each other (through resistors, perhaps), so that when the comparators are off, the nodes are free to assume voltages higher than the respective cell juncture, or up to 0.6V below, due to the body diode. Thus a signal injected into the resistor string will propagate through to the receiving optocoupler and indicate that all is well, but if any comparator is turned ON, the signal will be shunted into the rest of the pack, and the receiver will not see the signal. This circuit may require a diode in series with the comparator drain, so that the body diode cannot provide a current source to the string. 

I might do a simulation when I get the chance, but this is the OP's idea and he seems confident that it will work. I just want to see a complete simulation with two or more of the actual circuits and not a parametric block which may not be an accurate model.

Here is a simulation of my idea. It does show a drop in current through the series elements when the associated cell is above or below the limits, but it works better for the second cell and perfectly for the third. There may be an easy fix for this, but at least this is a full simulation, and I also supply the ASCII file if anyone wants to play with it and perhaps improve on the design. I still vote for the optocoupler from each battery (+) to the OR-ed outputs of the comparator. It only draws current when in a fault condition, which may be beneficial when the voltage is too high (by shunting current), but when below the lower limit the signal should disconnect the load, and when above, it should disconnect the charger. Since these are usually mutually exclusive, the same signal could be used for either condition. By adding another opto and separating the comparator outputs, two separate isolated signals could be provided.


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## PStechPaul (May 1, 2012)

Here is a simulation that works much better. It uses optocouplers on each unit, which can be connected to NMOS transistors if you want to replicate the behavior of the OP's circuit. The output section is limited by the voltage rating of the MOSFETs, but the zeners as shown can be added to limit the OFF voltage. However, this means that the current through the daisy chain will not go to essentially zero, but will be reduced by V(z)/V(pack). I show a 30V MOSFET with a 12V zener, and with only about 10V pack it does not come into play. And it also works with a Fairchild BSS123, which is a 100V part and costs $0.065/100. The LT6700-1, however, is a $2.50 part.


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## jddcircuit (Mar 18, 2010)

Paul,
I am struggling to see any advantage in your variations over the original design.

If cost is the driver then I think the TPS3700 is an equivalent to the LT6700. IIRC TPS3700 cost around $0.80 in quantity. 

The mosfet (ie BSS84) is around $0.03.


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## PStechPaul (May 1, 2012)

The TPS3700 is about $0.78 in 1000 piece quantity and $1.44 in 100s.
http://www.digikey.com/product-detail/en/TPS3700DDCR/296-30395-1-ND/3250123

If you really want to reduce cell load, consider that the TPS3700 has a constant current draw of 5.5 uA typical to 13 uA maximum, while the PIC12LF1822 is 8 to 19 uA at 3.0V and the PIC12F1822 at 5V is 32 to 66 uA. But it can be in sleep mode for 10 seconds and then operate for 100 mSec to take a reading, so the average current draw is less than 1 uA. The 1 Meg voltage divider takes about 3.5 uA as well, in either case.

I cannot see how your circuit works with a series string, although perhaps the element that is shunting the signal current also shifts all the voltages on the MOSFETs down so that the bottom element goes to zero. I would like to try a simulation to see how it works, so if you would supply your ASCII file I may try it. Perhaps I just don't particularly like PMOS and it goes against my preferences for the gate to be connected to GND.

[edit] Another refinement that could be added to the optocoupler/PIC design is that whichever module detects a fault could send a coded signal to the optocoupler which could contain information such as which cell it is, and its voltage. If all elements are in parallel or series, this will only work for a single fault. But an LED could be added which would give visual indication of each cell that has an error.

The daisy chain approach will work if each element receives an optically isolated signal from the one above it, or a master controller, and then passes the signal along, adding to it as needed. This does require perhaps 2 mA to drive the LED, but each packet would have a duration of perhaps 10-20 mSec and a repetition rate of 1-10 sec, so average current will be perhaps 5-10 uA.


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## jddcircuit (Mar 18, 2010)

PStechPaul said:


> The TPS3700 is about $0.78 in 1000 piece quantity and $1.44 in 100s.
> http://www.digikey.com/product-detail/en/TPS3700DDCR/296-30395-1-ND/3250123
> 
> If you really want to reduce cell load, consider that the TPS3700 has a constant current draw of 5.5 uA typical to 13 uA maximum, while the PIC12LF1822 is 8 to 19 uA at 3.0V and the PIC12F1822 at 5V is 32 to 66 uA. But it can be in sleep mode for 10 seconds and then operate for 100 mSec to take a reading, so the average current draw is less than 1 uA. The 1 Meg voltage divider takes about 3.5 uA as well, in either case.
> ...


I don't know what ascii file you are referring to nor why you think you need it. Just put the FETs in your simulation and see what you get.

Here is another example of how to evaluate the concept.
The blue signal represents the current source being applied at the most north cell module by the system controller.
The green signal is the voltage of cell #2 in the middle of the string. (this is made to vary to illustrate the function)
The red signal is the current that is making it to the end of chain.

You can see that the current (red signal) goes to zero if the cell voltage is out of range. This signal can be monitored by the controller to detect an out of range condition.









Good luck
Jeff


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## PStechPaul (May 1, 2012)

The ASCII file is how simulations are normally saved and shared in LTSpice. If you would provide it, it would be quick and simple for me or anyone to download it and use the program to open and run the simulation. It saves a lot of manual regeneration of the circuit and elements you have defined, and eliminates errors due to misreading what you have in your image (and it is not totally clear). 

I think I understand now how your circuit might work, but I do have some concerns about how certain portions might be implemented (such as the current source), and there are some things that are missing such as pull-up and pull-down resistors, and protective components. Not needed for the basic concept, though, but important for a real world implementation.


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## jddcircuit (Mar 18, 2010)

Paul,

The title of the thread is "concept" but real world implementation is the final objective so please share any suggestions or concerns you have with the concept or with implementation of the concept.

I think this type of current based daisy chain may have some merits.

If you suggest adding optos or micros to the design then please help me understand why. If it saves cost or improves performance I am open.

Perhaps this is the ltspice text file you need.
View attachment WOLS_Chain_Explained.txt


Thanks
Jeff


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## PStechPaul (May 1, 2012)

Yes! That's the file I needed to replicate your simulation. It looks OK, with the maximum Vds about 6.5V and normal current draw from each cell about 10 uA. I was wrong about needing a pull-up on the outputs of the LT6700. When the outputs are OFF, the gate of the MOSFET below is driven by the cell voltage. I think it would be good design practice to add a resistor from gate to source, and in series with the gate, to limit the effects of transients.

The implementation of a similar design using a small PIC seems advantageous because of cost, simplicity, and flexibility. A PIC12(L)F1822 is $0.82 in 100 piece quantity while the LT6700 is $2.46. The same MOSFETs (BSS84 $0.11) can be used to duplicate the performance of your circuit, if desired, eliminating the optoisolators. But the optos are only $0.25, and provide an extra measure of safety and versatility. The PIC12LF1822 provides a much lower current drain while in sleep mode (< 1uA operating current typical at 32 kHz), and it is possibly more universally available. 

I have made a PCB-ready design showing two units and their possible connections which can provide a means of daisy-chained communication with very low current draw, as well as variable (PWM) shunting for charge limiting, and optional optoisolator outputs for separate charger control. The PIC12LF1822 also has a USART which can be used for individual serial communication, including Bluetooth, I2C and SPI synchronous modules which can drive displays and other peripherals, and a temperature indicator module that can be used to adjust charging and over/under voltage settings based on temperature.

What's not to love?


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## jddcircuit (Mar 18, 2010)

Paul,
I can't make out the text in your schematic image. Could you post a higher resolution image?
Thanks
Jeff


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## PStechPaul (May 1, 2012)

I made the image a bit clearer. Also, here is a PDF that should be easy to read:

http://enginuitysystems.com/pix/BMS_12F1822_Simple.pdf

Hope this helps.


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